https://iopscience.iop.org/article/10.1088/1742-6596/1237/2/022009/pdf
위 논문 읽는 목적
: ultrasonic flowmeter의 고정밀 내부 HW logic design 을 알아보기 위함. 특히 시스템의 타이밍 기능을 완성하기 위해 CPU, DSP 및 FPGA를 한 칩에 통합하는 방법과 시스템의 통합성 및 안정성을 향상시키는 방법 등이 주요 관심사
Abstract: In order to improve the measurement accuracy of intelligent water meter, a high precision ultrasonic flowmeter is designed. The device integrates the functions of CPU, DSP and FPGA on one chip to complete the timing function, (하나의 칩에 통합하여 타이밍 기능을 완성하고, 이를 통해) which effectively improves the integration and stability of the system. The system uses time difference method to measure liquid velocity, and uses DSP Slices of Xilinx Corporation to complete smoothing filter function. The measurement accuracy is high and has a good application prospect.
*DSP Slices of Xilinx Corporation: DSP Slices는 Xilinx FPGA(Field-Programmable Gate Array)에서 사용되는 디지털 신호 처리(DSP)를 위한 특수한 하드웨어 블록
1. Introduction
With the increasing shortage of water resources in the world, governments all over the world attach great importance to water quantity control. At the same time, because of the rapid development of electronic technology, it is possible to meet the needs of intelligent water meters with step pricing. (단계적 가격 책정을 통한 지능형 수도계의 요구를 총족시킬 수 있게 되었다.)
(전통적인 mechanical water meter와 비교하여)
Compared with traditional mechanical water meter, intelligent water meter has the advantages of high accuracy, wide range ratio, long life, good reliability, no moving parts and flexible replacement. At present, the technology of ultrasonic flowmeter is widely used in intelligent water meters which can achieve high precision, and the principle of ultrasonic time difference measurement is generally used. Ultrasound time difference measurement uses multiple pairs of ultrasonic transducers to receive ultrasound simultaneously or alternately[1]. The velocity of fluid is measured by detecting the time difference between the propagating of ultrasound in the medium in both the downstream and the countercurrent, and then the flow rate is calculated by integrating the velocity with time.
(현재, 초음파 유속계는 지능형 water meter에서 널리 사용됨)
At present, the technology of ultrasonic flowmeter is widely used in intelligent water meters which can achieve high precision, and the principle of ultrasonic time difference measurement is generally used. (일반적으로 방법이 되게 많은데 일반적으로 time difference 방법 사용하나봄.)
Ultrasound time difference measurement uses multiple pairs of ultrasonic transducers to receive ultrasound simultaneously or alternately[1]. The velocity of fluid is measured by detecting the time difference between the propagating of ultrasound in the medium in both the downstream and the countercurrent, and then the flow rate is calculated by integrating the velocity with time.
* alternately: 번갈아가며
* countercurrent: 역류
2. Principle of the Ultrasonic Flowmeter
In Figure 1, the ultrasonic transducers A and B are respectively placed in the direction of downstream and countercurrent of the flowing liquid[2].
*respectively: 각각
In Figure 1, the time taken from transducer A to transducer B to receive ultrasound (초음파를 수신하기 위해) is
The time taken from transducer B to transducer A to receive ultrasound is:
Based on formula (1) and formula (2), it is found that the time difference in the direction of downstream and countercurrent propagation of ultrasound is as follows:
[참고]
- 식 (5)에서 수력학에 따라, 음속 경로의 평균 속도가 필요하다면 단면의 평균 속도로 추정됨 (K추가됐네)
- K는 유체 역학의 보정 계수이며, 이 계수는 원형 파이프의 저항 계수의 함수
- 람다는 유체의 레이놀즈 수의 함수
So the velocity of liquid flow is as follows: (따라서 유체의 속도는)
The liquid flow rate is as follows：(유체의 유량은)
3. Hardware Design
This design chooses FPGA designed by Xilinx corporation, which integrates Microblaze II processor and DSP Slices. It can realize the functions of FPGA, CPU and digital signal processer on a single chip. (이는 FPGA, CPU 및 digital signal processer의 기능을 단일 칩에 구현할 수 있다.)
(효과)
It effectively reduces the number of main control chips, and also reduces the number of connections between FPGA, CPU and DSP on board, because of which improves the stability of the system[4]. (이로써 주요 제어 칩의 수를 효과적으로 줄이고, 또한 보드 상의 FPGA, CPU 및 DSP 간의 연결 수를 줄임으로써 시스템의 안정성을 향상시킵니다[4].)
As shown in Figure 2, the hardwired logic of the FPGA controls the transmission and reception of ultrasonic by the ultrasonic module, and receives the signal from the ultrasonic module. After shaping and filtering, it is converted into digital signal which is transmitted to the DSP Slices of the FPGA through bus. The DSP Slices filters the input signal basing on smoothing filtering algorithm and sends the filtered signal to the Microblaze soft core, which displays the on LCD screen.
(그림 2에 나타난 것처럼, FPGA의 하드웨어 로직은 초음파 모듈을 통한 초음파의 송수신을 제어하고 초음파 모듈로부터 신호를 수신합니다. 모양을 만들고 필터링한 후, 이는 디지털 신호로 변환되어 버스를 통해 FPGA의 DSP 슬라이스로 전송됩니다. DSP 슬라이스는 입력 신호를 스무딩 필터링 알고리즘을 기반으로 필터링하고, 필터링된 신호를 Microblaze soft core로 전송하여 LCD 화면에 표시합니다.)
- 이분은 Xilinx FPGA 의 Microblaze II (Xilinx의 soft processor), DSP slice IP사용함 (이러한 IP를 사용해 FPGA 내에서 CPU 및 DSP를 효율적으로 수행가능)
3.1. Microblaze module
MicroBlaze is Xilinx’s 32-bit RISC soft processor core, optimized for embedded applications on Xilinx devices.
(MicroBlaze processor의 장점)
The MicroBlaze processor is easy to use and delivers the flexibility to select the combination of peripherals, memory, and interfaces as needed.
The MicroBlaze processor is commonly used in one of three preset configurations: a simple microcontroller running bare-metal applications; a real-time processor featuring cache and a memory protection unit interfacing to tightly coupled on-chip memory running FreeRTOS;
and finally, an application processor with a memory management unit running Linux.
MicroBlaze can be used as a stand-alone processor in all Xilinx FPGAs or as a co-processor in a Zynq®-7000 SoC system. ( MicroBlaze는 Xilinx 모든 FPGA에서 독립적인 프로세서로 또는 Zynq®-7000 SoC 시스템에서 공동 프로세서로 사용할 수 있습니다.)It can also be configured to add tamper protection and fault protection by configuring in lock-step mode as well as providing single-event upset mitigation with Triple Modular Redundancy. Designs with multiple processors can be debugged simultaneously using the Xilinx Software Development Kit (SDK).
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